| Abstract: |
The StrongARM latch remains the most widely deployed dynamic comparator in analog-to-digital converters, serial-link receivers and memory sense amplifiers, because it draws zero static current, restores rail-to-rail logic levels and needs only a single clock phase. Its migration into deeply scaled sub-32 nm nodes, however, has exposed a cluster of design tensions that two decades of literature have attacked from very different directions: random threshold-voltage mismatch that grows as device area shrinks, kickback noise injected into high-impedance sampling networks, metastability at multi-gigahertz sampling rates, and the loss of intrinsic gain caused by degraded output resistance and elevated gate and subthreshold leakage. This review consolidates that fragmented body of work into a single quantitative frame. Thirty primary studies published between 2004 and 2025 are surveyed and their reported figures of merit are normalised to a common basis so that a meta-analysis can be performed across technology nodes ranging from 180 nm down to 14 nm. Regression across the pooled dataset shows that energy per conversion falls with node dimension raised to a power of approximately 1.4, while input-referred offset standard deviation improves far more slowly and saturates near 6 mV once random dopant fluctuation and line-edge roughness dominate. Against this backdrop the paper examines a novel 20 nm StrongARM topology that combines a split tail with a charge-steering reset network and body-bias-assisted regeneration. Reported behaviour is compared with the surveyed corpus, the credibility of published claims is assessed, and open problems in calibration, variability modelling and benchmarking discipline are identified. |
